SH7014 Datasheet, PDF (678/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Timer Counter (TCNT)
H'FFFF8610 (Write)*¹
H'FFFF8611 (Read)*²
Bit
Item
7
6
5
4
3
2
Bit name
Initial value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: 1. Write by word transfer. It cannot be written in byte or longword.
2. Read by byte transfer. It cannot be read in word or longword.
WDT
―
1
0
0
0
R/W
R/W
Timer Control/Status Register (TCSR)
H'FFFF8610
―
Bit
Item
7
6
5
4
3
2
1
0
Bit name OVF
WT/IT
TME
―
―
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
R/W
R/(W)*
R/W
R/W
R
R
R/W
R/W
R/W
Note: * The TCSR differs from other registers in that it is more difficult to write to. See section 11.2.4,
Register Access, for details.
Bit
Name
7
Overflow Flag (OVF)
6
Timer Mode Select (WT/IT)
5
Timer Enable (TME)
Value
0
1
0
1
0
1
Description
No overflow of TCNT in interval timer mode (initial value)
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in the interval timer mode
Interval timer mode: interval timer interrupt request to the
CPU when TCNT overflows
(initial value)
Watchdog timer mode: WDTOVF signal output externally
when TCNT overflows*¹
Timer disabled: TCNT is initialized to H'00 and count-up
stops
(initial value)
Timer enabled: TCNT starts counting. A WDTOVF signal
or interrupt is generated when TCNT overflows.
Rev.5.00 Sep. 27, 2007 Page 644 of 716
REJ09B0398-0500