SH7014 Datasheet, PDF (93/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Processing
Section 5 Exception Processing
5.1 Overview
5.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority shown in table 5.1. When several exception processing sources occur at once,
they are processed according to the priority shown.
Table 5.1 Types of Exception Processing and Priority Order
Exception Source
Priority
Reset
Power-on reset
High
Address error CPU address error
DMAC address error
Interrupt NMI
User break
IRQ
On-chip peripheral modules: • Direct memory access controller (DMAC)
• Multifunction timer/pulse unit (MTU)
• Serial communication interface (SCI)
• A/D converter (A/D)
• Compare match timer (CMT)
• Watchdog timer (WDT)
• Bus state controller (BSC)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay branch Low
instruction*¹ or instructions that rewrite the PC*²)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.
Rev.5.00 Sep. 27, 2007 Page 59 of 716
REJ09B0398-0500