SH7014 Datasheet, PDF (457/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Compare Match Timer (CMT)
15.2.2 Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock
used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode.
Bit: 15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
CMF CMIE
⎯
⎯
⎯
⎯
CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/W
R
R
R
R
Note: * The only value that can be written is a 0 to clear the flag.
R/W R/W
Bits 15 to 8 and 5 to 2⎯Reserved: These bits always read as 0. The write value should always be
0.
Bit 7⎯Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and
CMCOR values have matched.
Bit 7
CMF
0
1
Description
CMCNT and CMCOR values have not matched
(initial status)
Clear condition: Write a 0 to CMF after reading a 1 from it
CMCNT and CMCOR values have matched
Bit 6⎯Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1).
Bit 6
CMIE
0
1
Description
Compare match interrupts (CMI) disabled
Compare match interrupts (CMI) enabled
(initial status)
Rev.5.00 Sep. 27, 2007 Page 423 of 716
REJ09B0398-0500