SH7014 Datasheet, PDF (255/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.2.7 Timer General Register (TGR)
Each timer general register (TGR) is a 16-bit register that can function as either an output compare
register or an input capture register. There are a total of eight TGR, four for channel 0, and two
each for channels 1 and 2. The TGRC and TGRD of channel 0 can be set to operate as buffer
registers. The TGR register and buffer register combinations are TGRA with TGRC, and TGRB
with TGRD.
The TGRs are initialized to H'FFFF by a power-on reset or in standby mode. Accessing of the
TGRs in 8-bit units is disabled; they may only be accessed in 16-bit units.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.8 Timer Start Register (TSTR)
The timer start register (TSTR) is an 8-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0 to 2. TSTR is initialized to H'00 upon power-on reset or standby
mode.
Bit: 7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
CST2 CST1 CST0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Rev.5.00 Sep. 27, 2007 Page 221 of 716
REJ09B0398-0500