SH7014 Datasheet, PDF (128/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
7.2 Register Explanation
7.2.1 Cache Control Register (CCR)
The cache control register (CCR) selects the cache enable/disable of each space.
The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is
not initialized by standby mode.
Bit: 15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value: *
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
⎯
⎯
⎯
CE
CE
CE
CE
CE
DRAM CS3 CS2 CS1 CS0
Initial value: *
*
*
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
Note: * Bits 15 to 5 are undefined.
Bits 15 to 5⎯Reserved: Reading these bits gives undefined values. The write value should
always be 0.
Bit 4⎯DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a
cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 4
CEDRAM
0
1
Description
DRAM space cache disabled
DRAM space cache enabled
(initial value)
Rev.5.00 Sep. 27, 2007 Page 94 of 716
REJ09B0398-0500