SH7014 Datasheet, PDF (299/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.5 Contention between Buffer Register Write and Compare Match
If a compare-match occurs in the T₂ state of the TGR write cycle, data is transferred by the buffer
operation from the buffer register to the TGR. Data to be transferred on channel 0 is that after
write (figure 10.52).
TGR write cycle
T₁
T₂
φ
Address
Buffer register
address
Write signal
Compare
match
signal
Compare
match buffer
signal
Buffer
register
Buffer register write data
N
M
TGR
M
Figure 10.52 TGR Write and Compare-Match Contention (Channel 0)
Rev.5.00 Sep. 27, 2007 Page 265 of 716
REJ09B0398-0500