SH7014 Datasheet, PDF (271/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
TCNT value
TGR0B
TGR0A
H'0000
H'0200
H'0450
TGR0C H'0200
Transfer
TGR0A
H'0200
H'0450
H'0520
H'0450
H'0520
Time
TIOC0A
Figure 10.19 Buffer Operation Example (Output Compare Register)
Buffer Operation Examples⎯when TGR Is an Input Capture Register: Figure 10.20 shows
an example of TGRA set as an input capture register with the TGRA and TGRC registers set for
buffer operation.
The TCNT counter is cleared by a TGRA register input capture, and the TIOCA pin input capture
input edge is selected as both rising and falling edge. Because buffer mode is selected, an input
capture A causes the TCNT counter value to be stored in the TGRA register, and the value that
was stored in the TGRA up until that time is simultaneously transferred to the TGRC register.
Rev.5.00 Sep. 27, 2007 Page 237 of 716
REJ09B0398-0500