SH7014 Datasheet, PDF (458/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Compare Match Timer (CMT)
Bits 1, 0⎯Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT
from among the four internal clocks obtained by dividing the system clock (φ). When the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and
CKS0.
Bit 1
CKS1
0
1
Bit 0
CKS0
0
1
0
1
Description
φ/8
φ/32
φ/128
φ/512
(initial status)
15.2.3 Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for
generating interrupt requests.
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT
value matches that of the compare match timer constant register (CMCOR), the CMCNT is
cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is
set to 1 at this time, a compare match interrupt (CMI) is requested.
The CMCNT is initialized to H'0000 by power-on resets and by standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev.5.00 Sep. 27, 2007 Page 424 of 716
REJ09B0398-0500