SH7014 Datasheet, PDF (397/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
12.5 Usage Notes
Sections 12.5.1 through 12.5.9 provide information for using the SCI.
12.5.1 TDR Write and TDRE Flags
The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data
from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can
be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is
0, however, the old data stored in TDR will be lost because the data has not yet been transferred to
the TSR. Before writing transmit data to the TDR, be sure to check that TDRE is set to 1.
12.5.2 Simultaneous Multiple Receive Errors
Table 12.13 indicates the state of the SSR status flags when multiple receive errors occur
simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to the
RDR, so receive data is lost.
Table 12.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
Receive Error Status
RDRF ORER FER PER
Overrun error
1
1
0
0
Framing error
0
0
1
0
Parity error
0
0
0
1
Overrun error + framing error
1
1
1
0
Overrun error + parity error
1
1
0
1
Framing error + parity error
0
0
1
1
Overrun error + framing error + parity error 1
1
1
1
Note: O = Receive data is transferred from RSR to RDR.
X = Receive data is not transferred from RSR to RDR.
Receive Data
Transfer
RSR → RDR
X
O
O
X
X
O
X
Rev.5.00 Sep. 27, 2007 Page 363 of 716
REJ09B0398-0500