SH7014 Datasheet, PDF (347/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
Bit 7⎯Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt request (TXI) is disabled* (initial value)
1
Transmit-data-empty interrupt request (TXI) is enabled
Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1,
then clearing TDRE to 0, or by clearing TIE to 0.
Bit 6⎯Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to
1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables receive-
error interrupt (ERI) requests.
Bit 6
RIE
Description
0
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are disabled*
(initial value)
1
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI)
requests are enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag
(FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by
clearing RIE to 0.
Bit 5⎯Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5
TE
Description
0
Transmitter disabled*¹
(initial value)
1
Transmitter enabled*²
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked
at 1.
2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial
status register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select
the transmit format in the SMR before setting TE to 1.
Rev.5.00 Sep. 27, 2007 Page 313 of 716
REJ09B0398-0500