SH7014 Datasheet, PDF (36/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

1. SH7014/16/17 Overview
⎯ Delayed branch instructions reduce pipeline disruption during branch
⎯ Instruction set based on C language
• Instruction execution time: one instruction/cycle (35 ns/instruction at 28.7-MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) and
multiplication/accumulation operations (32 bits × 32 bits + 64 bits → 64 bits) executed in two
to four cycles
• Five-stage pipeline
Cache Memory:
• 1-kbyte instruction cache
• Caching of instruction codes and PC relative read data
• 4-byte line length (1 longword: 2 instruction lengths)
• 256 entry cache tags
• Direct map method
• On-chip ROM/RAM, and on-chip I/O areas not objects of cache
• Used in common with on-chip RAM; 2 kbytes of on-chip RAM used as address array/data
array when cache is enabled
Interrupt Controller (INTC):
• Seven external interrupt pins (NMI, IRQ × 6)
• Twenty-eight internal interrupt sources
• Sixteen programmable priority levels
Bus State Controller (BSC):
• Supports external extended memory access
⎯ 8-bit, or 16-bit external data bus
• Memory address space divided into five areas (four areas of SRAM space, one area of DRAM
space) with the following settable features:
⎯ Number of wait cycles
⎯ Outputs chip-select signals for each area
⎯ During DRAM space access:
• Outputs RAS and CAS signals for DRAM
• Can generate a RAS precharge time assurance Tp cycle
Rev.5.00 Sep. 27, 2007 Page 2 of 716
REJ09B0398-0500