SH7014 Datasheet, PDF (668/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Timer Status Register 1 (TSR1)
H'FFFF8285
Bit
Item
7
6
5
4
3
2
Bit name TCFD
―
TCFU
TCFV
―
―
Initial value
1
1
0
0
0
0
R/W
R/W
R
R/(W)* R/(W)*
R
R
Note: * Only 0 writes to clear the flags are possible.
MTU
8/16/32
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Bit
7
5
4
1
0
Note: *
Name
Count Direction Flag (TCFD)
Underflow Flag (TCFU)
Overflow Flag (TCFV)
Input Capture/Output Compare
Flag B (TGFB)
Value
0
1
0
1
0
1
0
1
Input Capture/Output Compare
0
Flag A (TGFA)
1
Cleared by DMAC transfer due to TGFA.
Description
TCNT counts down
TCNT counts up
(initial value)
Clear condition: With TCFU = 1, a 0 write to TCFU
after reading it
(initial value)
Set condition: When the TCNT value underflows
(H'0000 → H'FFFF)
Clear condition: With TCFV = 1, a 0 write to TCFV
after reading it
(initial value)
Set condition: When the TCNT value overflows
(H'FFFF → H'0000)
Clear condition: With TGFB = 1, a 0 write to TGFB
following a read
(initial value)
Set conditions:
• When TGRB is functioning as an output compare
register (TCNT = TGRB)
• When TGRB is functioning as input capture (the
TCNT value is sent to TGRB by the input capture
signal)
Clear condition: With TGFA = 1, a 0 write to TGFA
following a read*
(initial value)
Set conditions:
• When TGRA is functioning as an output compare
register (TCNT = TGRA)
• When TGRA is functioning as input capture (the
TCNT value is sent to TGRA by the input capture
signal)
Rev.5.00 Sep. 27, 2007 Page 634 of 716
REJ09B0398-0500