SH7014 Datasheet, PDF (249/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Channels 1, 2: TIER1, TIER2
Bit: 7
6
TTGE ⎯
Initial value: 0
1
R/W: R/W
R
10. Multifunction Timer Pulse Unit (MTU)
5
4
3
TCIEU TCIEV ⎯
0
0
0
R/W R/W
R
2
1
0
⎯ TGIEB TGIEA
0
0
0
R
R/W R/W
Bit 7⎯A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an
A/D conversion start request by a TGRA register input capture/compare-match.
Bit 7
TTGE
0
1
Description
Disable A/D conversion start requests
Enable A/D conversion start request generation
(initial value)
Bit 6⎯Reserved: This bit always read as 1. The write value should always be 1.
Bit 5⎯Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the
underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1.
This bit is reserved for channel 0. It always reads as 0. The write value should always be 0.
Bit 5
TCIEU
0
1
Description
Disable UDF interrupt requests (TCIU)
Enable UDF interrupt requests (TCIU)
(initial value)
Bit 4⎯Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the
overflow flag TCFV of the timer status register (TSR) is set to 1.
Bit 4
TCIEV
0
1
Description
Disable TCFV interrupt requests (TCIV)
Enable TCFV interrupt requests (TCIV)
(initial value)
Rev.5.00 Sep. 27, 2007 Page 215 of 716
REJ09B0398-0500