SH7014 Datasheet, PDF (29/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14.1.2 Block Diagram ..................................................................................................... 398
14.1.3 Pin Configuration................................................................................................. 399
14.1.4 Register Configuration......................................................................................... 400
14.2 Register Descriptions ........................................................................................................ 401
14.2.1 A/D Data Register A to D (ADDRA to ADDRD) ............................................... 401
14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 402
14.2.3 A/D Control Register (ADCR) ............................................................................ 404
14.3 Interface with CPU............................................................................................................ 405
14.4 Operation........................................................................................................................... 407
14.4.1 Single Mode (SCAN = 0)..................................................................................... 407
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 409
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 411
14.4.4 MTU Trigger Input Timing.................................................................................. 413
14.5 Interrupt............................................................................................................................. 414
14.6 A/D Conversion Precision Definitions.............................................................................. 415
14.7 Usage Notes ...................................................................................................................... 417
14.7.1 Analog Voltage Settings ...................................................................................... 417
14.7.2 Handling of Analog Input Pins ............................................................................ 417
Section 15 Compare Match Timer (CMT) ................................................................... 419
15.1 Overview........................................................................................................................... 419
15.1.1 Features................................................................................................................ 419
15.1.2 Block Diagram ..................................................................................................... 419
15.1.3 Register Configuration......................................................................................... 421
15.2 Register Descriptions ........................................................................................................ 422
15.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 422
15.2.2 Compare Match Timer Control/Status Register (CMCSR).................................. 423
15.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 424
15.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 425
15.3 Operation........................................................................................................................... 426
15.3.1 Period Count Operation ....................................................................................... 426
15.3.2 CMCNT Count Timing........................................................................................ 426
15.4 Interrupts ........................................................................................................................... 427
15.4.1 Interrupt Sources.................................................................................................. 427
15.4.2 Compare Match Flag Set Timing......................................................................... 427
15.4.3 Compare Match Flag Clear Timing ..................................................................... 428
15.5 Usage Notes ...................................................................................................................... 429
15.5.1 Contention between CMCNT Write and Compare Match ................................... 429
15.5.2 Contention between CMCNT Word Write and Incrementation........................... 430
15.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 431
Rev.5.00 Sep. 27, 2007 Page xxix of xxxiv
REJ09B0398-0500