SH7014 Datasheet, PDF (251/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.2.5 Timer Status Register (TSR)
The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The
MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset
or by standby mode.
Channel 0: TSR0
Bit: 7
6
5
4
⎯
⎯
⎯
TCFV
Initial value: 1
1
0
0
R/W: R
R
R R/(W)*
Note: * Only 0 writes to clear the flags are possible.
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Channels 1, 2: TSR1, TSR2
Bit: 7
6
5
4
3
TCFD
⎯
TCFU TCFV
⎯
Initial value: 1
1
0
0
0
R/W: R
R R/(W)* R/(W)* R
Note: * Only 0 writes to clear the flags are possible.
2
1
0
⎯ TGFB TGFA
0
0
0
R R/(W)* R/(W)*
Bit 7⎯Count Direction Flag (TCFD): This status flag indicates the count direction of the
channel 1, 2 TCNT counters.
This bit is reserved in channel 0. This bit always reads as 1. The write value should always be 1.
Bit 7
TCFD
0
1
Description
TCNT counts down
TCNT counts up
(initial value)
Bit 6⎯Reserved: This bit always reads as 1. The write value should always be 1.
Rev.5.00 Sep. 27, 2007 Page 217 of 716
REJ09B0398-0500