SH7014 Datasheet, PDF (463/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Compare Match Timer (CMT)
15.5 Usage Notes
Take care that the contentions described in sections 15.5.1 to 15.5.3 do not arise during CMT
operation.
15.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T₂ state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
15.6 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 15.6 CMCNT Write and Compare Match Contention
Rev.5.00 Sep. 27, 2007 Page 429 of 716
REJ09B0398-0500