SH7014 Datasheet, PDF (659/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
MTU
Bit
Name
Value
Description
3 to 0 I/O Control C3 to C0 0 0 0 0 TGR0C is Output disabled
(initial value)
(IOC3 to IOC0)
1 ^{an output} Initial output is 0 Output 0 on compare-match
1
0
compare
register
Output 1 on compare-match
1
Toggle output on compare-
match
100
Output disabled
1
Initial output is 1 Output 0 on compare-match
10
Output 1 on compare-match
1
Toggle output on compare-
match
1 0 0 0 TGR0C is Capture input
1 ^{an input source is the}
1
0
capture
register
TIOC0C pin
1
Input capture on rising edge
Input capture on falling edge
Input capture on both edges
Notes:
100
Capture input Input capture on TCNT1
1
10
1
source is
channel 1/
count clock
count up/count down
1. When the BFB bit of TMDR0 is set to 1 and TGR0D is being used as a buffer register, these
settings become ineffective and input capture/output compares do not occur.
2. When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these
settings become ineffective and input capture/output compares do not occur.
Rev.5.00 Sep. 27, 2007 Page 625 of 716
REJ09B0398-0500