SH7014 Datasheet, PDF (654/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
MTU
Timer Control Register 0 (TCR0)
H'FFFF8260
8/16/32
Item
Bit name
Initial value
R/W
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
Bit
4
3
CKEG1 CKEG0
0
0
R/W
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Bit
Name
Value
Description
7 to 5 Counter Clear 2 to 0
(CCLR2 to CCLR0)
0 0 0 TCNT clear disabled
(initial value)
1 TCNT is cleared by TGRA compare-match or input
captur
1 0 TCNT is cleared by TGRB compare-match or input
capture
1 Synchronizing clear: TCNT is cleared in synchronization
with clear of other channel counters operating in sync.*¹
1 0 0 TCNT clear disabled
1 TCNT is cleared by TGRC compare-match or input
capture*²
1 0 TCNT is cleared by TGRD compare-match or input
capture*²
1 Synchronizing clear: TCNT is cleared in synchronization
with clear of other channel counters operating in sync*¹
4, 3 Clock Edge 1, 0
0
(CKEG1 and CKEG0)*⁴
0 Count on rising edges
1 Count on falling edges
(initial value)
1
X*³ Count on both rising and falling edges
2 to 0 Timer Prescaler 2 to 0
(TPSC2 to TPSC0)
0 0 0 Internal clock: count with φ/1
1 Internal clock: count with φ/4
(initial value)
1 0 Internal clock: count with φ/16
1 Internal clock: count with φ/64
1 0 0 External clock: count with the TCLKA pin input
1 External clock: count with the TCLKB pin input
1 0 External clock: count with the TCLKC pin input
1 External clock: count with the TCLKD pin input
Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.
2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because the buffer
registers have priority and compare-match/input captures do not occur.
3. X: 0 or 1, don't care.
4. Internal clock edge selection is effective when the input clock is φ/4 or slower. These settings are
ignored when φ/1, or the overflow/underflow of another channel is selected for the input clock.
Rev.5.00 Sep. 27, 2007 Page 620 of 716
REJ09B0398-0500