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| SH7014 Datasheet, PDF (40/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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1. SH7014/16/17 Overview
1.2 Block Diagram
Figure 1.1 is a block diagram of the SH7014. Figure 1.2 is a block diagram of the SH7016/17.
RES
WDTOVF
MD3
A15
MD2
A14
MD1
A13
MD0
NMI
EXTAL
XTAL
PLLVCC
A12
RAM (3 kB)/
cache (1 kB)
A11
A10
A9
A8
PLLCAP
A7
PLLVSS
VCC
VCC
A6
CPU
A5
Direct memory
A4
VCC
access controller
A3
VCC
A2
VCC
VSS
Interrupt
controller
Bus state controller
A1
A0
VSS
VSS
VSS
VSS
VSS
Serial communi-
cation interface
(Ã2 channels)
Multifunction timer/
pulse unit
D15
D14
D13
VSS
VSS
VSS
Compare match
timer (Ã2 channels)
A/D
Watch-
converter dog
timer
D12
D11
D10
VSS
D9
VSS
D8
AVCC
D7
AVSS
D6
D5
D4
D3
D2
D1
D0
: Peripheral address bus
: Peripheral data bus
: Internal address bus
: Internal upper data bus
: Internal lower data bus
Figure 1.1 Block Diagram of the SH7014
Rev.5.00 Sep. 27, 2007 Page 6 of 716
REJ09B0398-0500
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