SH7014 Datasheet, PDF (237/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Channel 2
Bit 2 Bit 1 Bit 0
TPSC2 TPSC1 TPSC0 Description
0
0
0
Internal clock: count with φ/1
1
Internal clock: count with φ/4
1
0
Internal clock: count with φ/16
1
Internal clock: count with φ/64
1
0
0
External clock: count with the TCLKA pin input
1
External clock: count with the TCLKB pin input
1
0
External clock: count with the TCLKC pin input
1
Internal clock: count with φ/1024
Note: These settings are ineffective when channel 2 is in phase counting mode.
(initial value)
10.2.2 Timer Mode Register (TMDR)
The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU
has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset
or the standby mode.
Channel 0: TMDR0
Bit: 7
⎯
Initial value: 1
R/W: R
6
5
4
3
2
1
0
⎯
BFB BFA MD3 MD2 MD1 MD0
1
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Channels 1, 2: TMDR1, TMDR2
Bit: 7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
MD3 MD2 MD1 MD0
Initial value: 1
1
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
Rev.5.00 Sep. 27, 2007 Page 203 of 716
REJ09B0398-0500