SH7014 Datasheet, PDF (648/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
BSC
Refresh Timer Control/Status Register (RTCSR)
H'FFFF862C
8/16/32
Item
15
Bit name
―
Initial value
0
R/W
R
Item
7
Bit name
―
Initial value
0
R/W
R
14
―
0
R
6
CMF
0
R/W
13
―
0
R
5
CMIE
0
R/W
Bit
12
11
―
―
0
0
R
R
4
3
CKS2
CKS1
0
0
R/W
R/W
10
―
0
R
2
CKS0
0
R/W
9
―
0
R
1
RFSH
0
R/W
8
―
0
R
0
RMD
0
R/W
Bit
6
5
4 to 2
1
0
Name
Compare Match Flag (CMF)
Compare Match Interrupt
Enable (CMIE)
Clock Select (CKS2 to CKS0)
Refresh Control (RFSH)
Refresh Mode (RMD)
Value
0
1
0
1
000
1
10
1
100
1
10
1
0
1
0
1
Description
Clear condition: After RTCSR is read when CMF is
1, 0 is written in CMF
(initial value)
Set condition: RTCNT = RTCOR
Note: When both RTCNT and RTCOR are in an
initialized state (when values have not been
rewritten since initialization, and RTCNT has
not had its value changed due to a countup),
RTCNT and RTCOR match, as both are
H'0000, but in this case CMF is not set.
Disables an interrupt request caused by CMF
(initial value)
Enables an interrupt request caused by CMF
Stops count-up
(initial value)
φ/2
φ/8
φ/32
φ/128
φ/512
φ/2048
φ/4096
Do not refresh DRAM
(initial value)
Refresh DRAM
CAS-before-RAS refresh
(initial value)
Self-refresh
Rev.5.00 Sep. 27, 2007 Page 614 of 716
REJ09B0398-0500