SH7014 Datasheet, PDF (350/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
12.2.7 Serial Status Register (SSR)
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a power-on reset or in standby mode.
Bit: 7
6
5
4
3
TDRE RDRF ORER FER PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit 7⎯Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from the TDR into the TSR and new serial transmit data can be written in the TDR.
Bit 7
TDRE
0
1
Description
TDR contains valid transmit data
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When DMAC writes data in TDR
TDR does not contain valid transmit data
[Setting conditions]
(initial value)
• Power-on reset or standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Rev.5.00 Sep. 27, 2007 Page 316 of 716
REJ09B0398-0500