SH7014 Datasheet, PDF (326/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Watchdog Timer (WDT)
11.1.2 Block Diagram
Figure 11.1 is the block diagram of the WDT.
ITI
(interrupt
signal)
WDTOVF
Internal
reset signal*
Interrupt
control
Overflow
Reset
control
Clock
Clock
select
φ/2
φ/64
φ/128
φ/256
φ/512
φ/1024
φ/4096
φ/8192
Internal
clock sources
RSTCSR
TCNT
TCSR
Module bus
Bus
interface
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Note: * The internal reset signal can be generated by setting the register.
Figure 11.1 WDT Block Diagram
11.1.3 Pin Configuration
Table 11.1 shows the pin configuration.
Table 11.1 Pin Configuration
Pin
Abbreviation I/O
Watchdog timer overflow WDTOVF
O
Function
Outputs the counter overflow signal in the
watchdog timer mode
Rev.5.00 Sep. 27, 2007 Page 292 of 716
REJ09B0398-0500