SH7014 Datasheet, PDF (137/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.1.3 Pin Configuration
Table 8.1 shows the bus state controller pin configuration.
Table 8.1 Pin Configuration
Signal
I/O Description
A21 to A0
O Address output (A21 to A18 become input ports in power-on reset)
D15 to D0
I/O 16-bit data bus. D15-D0 are address output and data I/O during
address/data multiplex I/O.
CS0 to CS3 O Chip select
RD
O Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also
output during DRAM access.
WRH
O Strobe that indicates a write cycle to the higher byte (D15 to D8) for
ordinary space/multiplex I/O. Also output during DRAM access.
WRL
O Strobe that indicates a write cycle to the lower byte (D7 to D0) for ordinary
space/multiplex I/O. Also output during DRAM access.
RDWR
O Strobe indicating a write cycle to DRAM (used for DRAM space)
RAS
O RAS signal for DRAM (used for DRAM space)
CASH
O CAS signal when accessing the higher byte (D15 to D8) of DRAM (used
for DRAM space)
CASL
O CAS signal when accessing the lower byte (D7 to D0) of DRAM (used for
DRAM space)
AH
O Signal to hold the address during address/data multiplex
WAIT
I
Wait state request signal
8.1.4 Register Configuration
The BSC has eight registers. These registers are used to control wait states, bus width, and
interfaces with memories like DRAM, SRAM, and ROM, as well as refresh control. The register
configurations are listed in table 8.2.
All registers are 16 bits. Do not access DRAM space before completing the memory interface
settings. All BSC registers are all initialized by a power-on reset. Values are maintained in standby
mode.
Rev.5.00 Sep. 27, 2007 Page 103 of 716
REJ09B0398-0500