SH7014 Datasheet, PDF (306/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set .
Figure 10.59 shows the operation timing in this case.
TCNT write cycle
T1
T2
φ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
H'FFFF
N
TCNT write data
TCFV flag
Disabled
Figure 10.59 Contention between TCNT Write and Overflow
10.7.13 Cautions on Carrying Out Buffer Operation of Channel 0 in PWM Mode 1
In PWM mode 1, the TGRA and TGRB registers are used in pairs and PWM waveform is output
to the TIOCA pin. In the same manner, the TGRC and TGRD registers are used in pairs and PWM
waveform is output to the TIOCC pin. If either the TGRC or TGRD register is operating as a
buffer register, the TIOCC pin cannot execute default output setting or PWM waveform output
with the I/O control register (TIOR).
Note that for channel 0, the TIOCC pin allows both default output setting by TIOR and PWM
output when setting buffer operation only for the TGRD register in PWM mode 1.
When using channel 0 in PWM mode 1 and setting buffer operation, use both the TGRC and
TGRD registers as buffer registers.
Rev.5.00 Sep. 27, 2007 Page 272 of 716
REJ09B0398-0500