SH7014 Datasheet, PDF (661/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
MTU
Timer Status Register 0 (TSR0)
H'FFFF8265
Bit
Item
7
6
5
4
3
Bit name
―
―
―
TCFV
TGFD
Initial value
1
1
0
0
0
R/W
R
R
R
R/(W)* R/(W)*
Note: * Only 0 writes to clear the flags are possible.
2
TGFC
0
R/(W)*
8/16/32
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Bit
Name
4
Overflow Flag (TCFV)
3
Input Capture/Output Compare
Flag D (TGFD)
2
Input Capture/Output Compare
Flag C (TGFC)
1
Input Capture/Output Compare
Flag B (TGFB)
Value
0
1
0
1
0
1
0
1
Description
Clear condition: With TCFV = 1, a 0 write to TCFV
after reading it
(initial value)
Set condition: When the TCNT value overflows
(H'FFFF → H'0000)
(initial value)
Clear condition: With TGFD = 1, a 0 write to TGFD
following a read
(initial value)
Set conditions:
• When TGRD is functioning as an output compare
register (TCNT = TGRD)
• When TGRD is functioning as input capture (the
TCNT value is sent to TGRD by the input capture
signal)
Clear condition: With TGFC = 1, a 0 write to TGFC
following a read
(initial value)
Set conditions:
• When TGRC is functioning as an output compare
register (TCNT = TGRC)
• When TGRC is functioning as input capture (the
TCNT value is sent to TGRC by the input capture
signal)
Clear condition: With TGFB = 1, a 0 write to TGFB
following a read
(initial value)
Set conditions:
• When TGRB is functioning as an output compare
register (TCNT = TGRB)
• When TGRB is functioning as input capture (the
TCNT value is sent to TGRB by the input capture
signal)
Rev.5.00 Sep. 27, 2007 Page 627 of 716
REJ09B0398-0500