SH7014 Datasheet, PDF (184/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Direct Memory Access Controller (DMAC)
9.1.4 Register Configuration
Table 9.2 summarizes the DMAC registers. DMAC has a total of 9 registers. Each channel has
four control registers. One other control register is shared by all channels.
Table 9.2 DMAC Registers
Channel Name
Abbrevi-
Initial
ation
R/W Value
Address
Register Access
Size
Size
0
DMA source
SAR0
R/W Undefined H'FFFF86C0 32 bit 16, 32*²
address register 0
DMA destination DAR0
address register 0
R/W Undefined H'FFFF86C4 32 bit 16, 32*²
DMA transfer count DMATCR0 R/W Undefined H'FFFF86C8 32 bit
register 0
16, 32*³
DMA channel
CHCR0 R/W*¹ H'00000000 H'FFFF86CC 32 bit
control register 0
16, 32*²
1
DMA source
SAR1
R/W Undefined H'FFFF86D0 32 bit 16, 32*²
address register 1
DMA destination DAR1
address register 1
R/W Undefined H'FFFF86D4 32 bit 16, 32*²
DMA transfer count DMATCR1 R/W Undefined H'FFFF86D8 32 bit
register 1
16, 32*³
DMA channel
CHCR1 R/W*¹ H'00000000 H'FFFF86DC 32 bit
control register 1
16, 32*²
Shared DMA operation
register
DMAOR R/W*¹ H'0000
H'FFFF86B0 16 bit 16*⁴
Notes: 1. Write 0 after reading 1 in bit 1 of CHCR0, CHCR1 and in bits 1 and 2 of the DMAOR to
clear flags. No other writes are allowed.
2. For 16-bit access of SAR0, SAR1, DAR0, DAR1, and CHCR0, CHCR1, the 16-bit value
on the side not accessed is held.
3. DMATCR has a 16-bit configuration: bits 0 to 15. Writing to the upper 16 bits (bits 16 to
31) is invalid, and these bits always read 0.
4. Only 16-bit access for DMAOR.
5. Do not attempt to access an empty address. If an access is attemped, the system
operation is not guarenteed.
Rev.5.00 Sep. 27, 2007 Page 150 of 716
REJ09B0398-0500