SH7014 Datasheet, PDF (182/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Direct Memory Access Controller (DMAC)
9.1.2 Block Diagram
Figure 9.1 is a block diagram of the DMAC.
On-chip ROM*
On-chip RAM
On-chip
peripheral
module
DMAC module
Circuit
control
SARn
Register
control
Activation
control
DARn
DMATCRn
CHCRn
DREQ0, DREQ1
MTU
SCI0, SCI1
A/D converter
DEIn
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
Request
priority
control
DMAOR
Bus interface
Bus state
controller
Legend:
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DMAOR: DMAC operation register
Notes: n = 0, 1
* SH7016, SH7017 only
Figure 9.1 DMAC Block Diagram
Rev.5.00 Sep. 27, 2007 Page 148 of 716
REJ09B0398-0500