SH7014 Datasheet, PDF (261/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
To select the counting operation (figure 10.6):
1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock. At the same time, set bits
CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock.
2. To operate as a periodic counter, set the CCLR2 to CCLR0 bits in the TCR to select TGR as a
clearing source for the TCNT.
3. Set the TGR selected in step 2 as an output compare register using the timer I/O control
register (TIOR).
4. Write the desired cycle value in the TGR selected in step 2.
5. Set the CST bit in the TSTR to 1 to start counting.
Counting mode selection
Select counter clock
1
Periodic counter
Select counter
clear source
Select output
compare register
Free-running counter
2
3
Set period
4
Start counting
Periodic counter
5
Start counting
5
Free-running counter
Figure 10.6 Procedure for Selecting the Counting Operation
Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves
them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer
counter operates as a free-running counter and begins to increment. When the count overflows
from H'FFFF to H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV
bit in the timer's corresponding timer interrupt enable register (TIER) is set to 1, the MTU will
make an interrupt request to the interrupt controller. After the TCNT overflows, counting
continues from H'0000. Figure 10.7 shows an example of free-running counter operation.
Rev.5.00 Sep. 27, 2007 Page 227 of 716
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