SH7014 Datasheet, PDF (435/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯
14.2 Register Descriptions
14.2.1 A/D Data Register A to D (ADDRA to ADDRD)
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRn : AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W : R R R R R R R R R R R R R R R R
Note: n = A to D
A/D registers are special registers that read stored results of A/D conversion in 16 bits. There are
four registers: ADDRA to ADDRD.
The A/D converted data is 10 bit data which is to the ADDR of the corresponding converted
channel for storage. The upper 8 bits of the A/D converted data correspond to the upper byte of the
ADDR and the lower 2 bits correspond to the lower byte. Bits 5 to 0 of the lower byte of ADDR
are reserved and always read 0. Analog input channels and correspondence to ADDR are shown in
table 14.3.
ADDR can always be read from the CPU. The upper byte may be read directly. The lower byte is
transferred through the temporary register (TEMP). For details, see section 14.3, Interface with
CPU.
ADDR is initialized to H'0000 during power-on reset.
Table 14.3 Analog Input Channel and ADDRA to ADDRD Correspondence
Group
AN0
AN1
AN2
AN3
Analog Input Channel
Group 1
AN4
AN5
AN6
AN7
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev.5.00 Sep. 27, 2007 Page 401 of 716
REJ09B0398-0500