SH7014 Datasheet, PDF (238/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Bits 7 and 6⎯Reserved: These bits always read as 1. The write value should always be 1.
Bit 5⎯Buffer Operation B (BFB): Designates whether to use the TGRB register for normal
operation, or buffer operation in combination with the TGRD register. When using TGRD as a
buffer register, no TGRD register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRD registers. This bit always read as 0.
The write value should always be 0.
Bit 5
BFB
0
1
Description
TGRB operates normally
TGRB and TGRD buffer operation
(initial value)
Bit 4⎯Buffer Operation A (BFA): Designates whether to use the TGRA register for normal
operation, or buffer operation in combination with the TGRC register. When using TGRC as a
buffer register, no TGRC register input capture/output compares are generated.
This bit is reserved in channels 1 and 2, which have no TGRC registers. This bit always read as 0.
The write value should always be 0.
Bit 4
BFA
0
1
Description
TGRA operates normally
TGRA and TGRC buffer operation
(initial value)
Rev.5.00 Sep. 27, 2007 Page 204 of 716
REJ09B0398-0500