SH7014 Datasheet, PDF (684/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Serial Status Register (SSR)
H'FFFF81A4 (Channel 0)
H'FFFF81B4 (Channel 1)
Bit
Item
7
6
5
4
3
Bit name TDRE
RDRF
ORER
FER
PER
Initial value
1
0
0
0
0
R/W
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
SCI
8/16
1
MPB
0
R
0
MPBT
0
R/W
Bit
Name
Value
Description
7
Transmit Data Register Empty 0 TDR contains valid transmit data
(TDRE)
Clearing conditions:
• When 0 is written to TDRE after reading TDRE = 1
• When DMAC writes data in TDR
1 TDR does not contain valid transmit data (initial value)
Setting conditions:
• Power-on reset or standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data
can be written to TDR
6
Receive Data Register Full
(RDRF)
0 RDR does not contain valid received data (initial value)
Clearing conditions:
• Power-on reset or standby mode
• When 0 is written to RDRF after reading RDRF = 1
• When DMAC reads data from RDR
1 RDR contains valid received data
Setting condition: When serial reception ends normally
and receive data is transferred from RSR to RDR
Rev.5.00 Sep. 27, 2007 Page 650 of 716
REJ09B0398-0500