SH7014 Datasheet, PDF (151/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
Bit 7⎯DRAM Idle Cycle Count (DIW): Specifies whether to insert idle cycles, either when
accessing a different external space (CS space) or when doing a DRAM write, after DRAM reads.
Bit 7
DIW
0
1
Description
No idle cycles
1 idle cycle
(initial value)
Bit 6⎯Reserved: This bit always read as 0. The write value should always be 0.
Bit 5⎯Burst Enable (BE): Specifies the DRAM operation mode.
Bit 5
BE
0
1
Description
Burst disabled
DRAM high-speed page mode enabled.
(initial value)
Bit 4⎯RAS Down Mode (RASD): Specifies the DRAM operation mode.
Bit 4
RASD
0
1
Description
Access DRAM by RAS up mode
Access DRAM by RAS down mode
(initial value)
Bit 3⎯Reserved: This bit read 0 after a reset. The write value should always be 0. Operation is
not guaranteed if the write value is 1.
Bit 2⎯DRAM Bus Width Specification (SZ0): Specifies the DRAM space bus width.
Bit 2
SZ0
0
1
Description
Byte (8-bit)
Word (16-bit)
(initial value)
Rev.5.00 Sep. 27, 2007 Page 117 of 716
REJ09B0398-0500