SH7014 Datasheet, PDF (234/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Bits 7 to 5⎯Counter Clear 2 to 0 (CCLR2 to CCLR0): Select the counter clear source for the
TCNT counter.
Channels 0
Bit 7 Bit 6 Bit 5
CCLR2 CCLR1 CCLR0 Description
0
0
0
TCNT clear disabled
(initial value)
1
TCNT is cleared by TGRA compare-match or input capture
1
0
TCNT is cleared by TGRB compare-match or input capture
1
Synchronizing clear: TCNT is cleared in synchronization with clear of
other channel counters operating in sync.*¹
1
0
0
TCNT clear disabled
1
TCNT is cleared by TGRC compare-match or input capture*²
1
0
TCNT is cleared by TGRD compare-match or input capture*²
1
Synchronizing clear: TCNT is cleared in synchronization with clear of
other channel counters operating in sync*¹
Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.
2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because
the buffer registers have priority and compare-match/input captures do not occur.
Channels 1, 2
Bit 7
Bit 6
Bit 5
Reserved*¹ CCLR1 CCLR0 Description
0
0
0
TCNT clear disabled
(initial value)
1
TCNT is cleared by TGRA compare-match or input capture
1
0
TCNT is cleared by TGRB compare-match or input capture
1
Synchronizing clear: TCNT is cleared in synchronization with
clear of other channel counters operating in sync*²
Notes: 1. The bit 7 of channels 1 and 2 is reserved. It always reads 0, and cannot be modified.
2. Setting the SYNC bit of the TSYR to 1 sets the synchronization.
Rev.5.00 Sep. 27, 2007 Page 200 of 716
REJ09B0398-0500