SH7014 Datasheet, PDF (343/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR.
The CPU cannot read or write the TSR directly.
12.2.4 Transmit Data Register (TDR)
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the
TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset
or in standby mode.
12.2.5 Serial Mode Register (SMR)
Bit: 7
C/A
Initial value: 0
R/W: R/W
6
5
CHR
PE
0
0
R/W R/W
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset
or in standby mode.
Rev.5.00 Sep. 27, 2007 Page 309 of 716
REJ09B0398-0500