SH7014 Datasheet, PDF (9/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
8.2.5 DRAM Area
115
Control Register (DCR)
9.1.1 Features
147
9.2.3 DMA Transfer 153
Count Registers 0, 1
(DMATCR0, DMATCR1)
9.3.5 Number of Bus 176
Cycle States and DREQ
Pin Sample Timing
Cycle Steal Mode
Operations:
Figure 9.12 Cycle
Steal, Single Address
and Level Detection
(Normal Operation)
Burst Mode, Single
185
Address, and Edge
Detection:
Revision (See Manual for Details)
Description amended
DCR is a 16-bit read/write register that selects the number of
waits, operation mode, number of address multiplex shifts and
the like for DRAM control.
After a power-on reset, write the initial values to the bits in DCR
and do not change the values afterward.
Do not perform any DRAM space accesses before DCR initial
settings are completed.
Description amended
• Transfer requests: There are three DMAC transfer activation
requests, as indicated below.
⎯ External request: From two DREQ pins. DREQ can be
detected either by falling edge or by low level. These
can be received by all channels.
Description amended
… Specifying a H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 65,536 transfers. While
DMAC is in operation, the number of transfers to be performed
is indicated. The initial value after power-on resets or in
software standby mode is undefined.
Upper sixteen bits of this register are read as 0 and the write
value should always be 0.
Note added
Note: With cycle-steal and single address operation, sampling
timing is the same whether DREQ detection is by level
or by edge.
Description amended
…During this period, data is undefined, and DACK is not
output. Nor is the number of DMAC transfers counted. The
actual DMAC transfer begins after one dummy bus cycle
output. Thereafter, DMAC transfer continues until the data
transfer count set in the DMATCR has ended. ...
Rev.5.00 Sep. 27, 2007 Page ix of xxxiv
REJ09B0398-0500