SH7014 Datasheet, PDF (122/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
6.5 Interrupt Response Time
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is
accepted.
Table 6.5 Interrupt Response Time
Number of States
Item
NMI, Peripheral
Module
IRQ
Notes
DMAC active judgment 0 or 1
1
1 state required for interrupt
signals for which DMAC
activation is possible
Compare identified inter- 2
3
rupt priority with SR mask
level
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
Interrupt
response
time
Total: 7 + m1 + m2 + m3
Minimum: 10
Maximum: 12 + 2 (m1 + m2 +
m3) + m4
9 + m1 + m2 + m3
12
13 + 2 (m1 + m2 +
m3) + m4
Performs the PC and SR
saves and vector address
fetch.
0.35 to 0.42 μs at 28.7 MHz
0.67 to 0.70 μs at 28.7
MHz*
Note:
When m1 = m2 = m3 = m4 = 1
m1 to m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev.5.00 Sep. 27, 2007 Page 88 of 716
REJ09B0398-0500