SH7014 Datasheet, PDF (177/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.7 Bus Arbitration
It has two internal bus masters, the CPU and the DMAC. The priority ranking for determining bus
right transfer between these bus masters is:
Refresh > DMAC > CPU
8.8 Memory Connection Examples
Figures 8.22 to 8.27 show examples of the memory connections.
As A21 to A18 become input ports in power-on reset, they should be handled (e.g.
pulled down) as necessary.
SH7014/16/17
CSn
RD
A0 to A14
D0 to D7
32 k × 8 bits
ROM
CE
OE
A0 to A14
I/O0 to I/O7
Figure 8.22 8-Bit Data Bus Width ROM Connection
SH7014/16/17
CSn
RD
A0
A1 to A18
D0 to D15
256 k × 16 bits
ROM
CE
OE
A0 to A17
I/O0 to I/O15
Figure 8.23 16-Bit Data Bus Width ROM Connection
Rev.5.00 Sep. 27, 2007 Page 143 of 716
REJ09B0398-0500