SH7014 Datasheet, PDF (79/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Table 2.17 System Control Instructions
Instruction
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RTE
Instruction Code
0000000000001000
0000000000101000
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000000101011
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STS MACH,Rn
STS MACL,Rn
STS PR,Rn
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
Operation
Exec.
Cycles
0→T
1
0 → MACH, MACL
1
Rm → SR
1
Rm → GBR
1
Rm → VBR
1
(Rm) → SR, Rm + 4 → Rm 3
(Rm) → GBR, Rm + 4 → Rm 3
(Rm) → VBR, Rm + 4 → Rm 3
Rm → MACH
1
Rm → MACL
1
Rm → PR
1
(Rm) → MACH, Rm + 4 → Rm 1
(Rm) → MACL, Rm + 4 → Rm 1
(Rm) → PR, Rm + 4 → Rm 1
No operation
1
Delayed branch, stack area 4
→ PC/SR
1→T
1
Sleep
3*
SR → Rn
1
GBR → Rn
1
VBR → Rn
1
Rn − 4 → Rn, SR → (Rn)
2
Rn − 4 → Rn, GBR → (Rn) 2
Rn − 4 → Rn, BR → (Rn)
2
MACH → Rn
1
MACL → Rn
1
PR → Rn
1
T Bit
0
⎯
LSB
⎯
⎯
LSB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Rev.5.00 Sep. 27, 2007 Page 45 of 716
REJ09B0398-0500