SH7014 Datasheet, PDF (445/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Mid-Speed A/D Converter ⎯ SH7016, SH7017 ⎯
14.4.3 Input Sampling and A/D Conversion Time
The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D
converter samples input after t_D hours has elapsed since setting the ADST bit of the A/D
control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is
shown in table 14.4.
The A/D conversion time, as shown in figure 14.5, includes both t_D and input sampling time. Here,
t_D is determined by the write timing to ADCSR and is not constant. Thus the conversion time
changes in the range shown in table 14.4.
The conversion time shown in table 14.4 is the time for the first conversion. For the second
conversion and after, the time will be 256 state (fixed) for CKS = 0 and 128 state (fixed) for CKS
= 1.
Rev.5.00 Sep. 27, 2007 Page 411 of 716
REJ09B0398-0500