SH7014 Datasheet, PDF (144/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
Bit 13
IW21
0
1
Bit 12
IW20
0
1
0
1
Description
No idle cycle after accessing CS2 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(initial value)
Bit 11
IW11
0
1
Bit 10
IW10
0
1
0
1
Description
No idle cycle after accessing CS1 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(initial value)
Bit 9
IW01
0
1
Bit 8
IW00
0
1
0
1
Description
No idle cycle after accessing CS0 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(initial value)
Bits 7 to 4⎯Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by once
negating the CSn signal when doing consecutive accesses of the same CS space. When a write
immediately follows a read, the number of idle cycles inserted is the larger of the two values
specified by IW and CW. Refer to section 8.6, Waits between Access Cycles, for details.
CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access
idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies
the continuous access idles for CS0 space.
Bit 7
CW3
0
1
Description
No CS3 space continuous access idle cycles
One CS3 space continuous access idle cycle
(initial value)
Rev.5.00 Sep. 27, 2007 Page 110 of 716
REJ09B0398-0500