SH7014 Datasheet, PDF (589/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Power-Down State
Table 21.3 Register States in the Standby Mode
Module
Registers Initialized
Registers that Registers with
Retain Data Undefined Contents
Interrupt controller ⎯
(INTC)
All registers
⎯
Cache memory (CAC) ⎯
All registers
⎯
Bus state controller ⎯
(BSC)
All registers
⎯
Direct memory access • DMA channel control
⎯
controller (DMAC)
registers 0, 1 (CHCR0,
CHCR1)
• DMA source
address registers
0, 1 (SAR0, SAR1)
• DMA operation register
(DMAOR)
• DMA destination
address registers
0, 1 (DAR0, DAR1)
• DMA transfer count
registers 0, 1
(DMATCR0,
DMATCR1)
Multifunction timer MTU associated registers
⎯
⎯
pulse unit (MTU)
Watchdog timer
(WDT)
• Bits 7 to 5 (OVF, WT/IT, TME) • Bits 2 to 0 ⎯
of the timer control status
(CKS2 to
register (TCSR)
CKS0) of the
• Reset control/status register
TCSR
(RSTCSR)
• Timer counter
(TCNT)
Serial communication • Receive data register (RDR) ⎯
⎯
interface (SCI)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
A/D converter (A/D) All registers
⎯
⎯
Compare match timer All registers
(CMT)
⎯
⎯
Pin function controller ⎯
(PFC)
All registers
⎯
Rev.5.00 Sep. 27, 2007 Page 555 of 716
REJ09B0398-0500