SH7014 Datasheet, PDF (297/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.3 Contention between TCNT Write and Clear
If a counter clear signal is issued in the T₂ state during the TCNT write cycle, TCNT clearing has
priority, and TCNT write is not conducted (figure 10.50).
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
Counter
clear signal
TCNT
N
H'0000
Figure 10.50 TCNT Write and Clear Contention
Rev.5.00 Sep. 27, 2007 Page 263 of 716
REJ09B0398-0500