SH7014 Datasheet, PDF (10/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
9.3.6 DMA Transfer 187
Ending Conditions
Conditions for Ending All
Channels
Simultaneously:
9.4.2 Example of DMA 189
Transfer between
External RAM and
External Device with
DACK
10.1.1 Features
191
10.1.4 Register
198
Configuration
Table 10.3 Register
Configuration
10.2.4 Timer Interrupt 215
Enable Register (TIER)
Bit 5—Underflow
Interrupt Enable
(TCIEU)
Bit 3—TGR Interrupt 216
Enable D (TGIED):
Bit 2—TGR Interrupt
Enable C (TGIEC):
10.2.5 Timer Status 217
Register (TSR)
Revision (See Manual for Details)
Description amended
When the processing of a one unit transfer is complete. In a
dual address mode direct address transfer, even if an address
error occurs or the NMI flag is set during read processing, the
transfer will not be halted until after completion of the following
write processing. In such a case, SAR, DAR, and DMATCR
values are updated.
Description amended
In this example, an external request, single address mode
transfer with external memory as the transfer source and an
external device with DACK as the transfer destination is
executed using DMAC channel 1.
Description amended
⎯ PWM mode: PWM output can be provided with any duty
cycle. When combined with the counter synchronizing
function, up to seven-phase PWM output is enabled
(with channels 0 to 2 set to PWM mode 2 and channel 0
synchronized with the TGR0A register (channels 0 to 2
phase output: 3, 2, 2)).
Notes amended
Notes: Do not access empty addresses.
1. 16-bit registers (TCNT, TGR) cannot be read or
written in 8-bit units.
2. Write 0 to clear flags.
Description amended
This bit is reserved for channel 0. It always reads as 0. The
write value should always be 0.
Description amended
This bit is reserved for channels 1 and 2. It always reads as 0.
The write value should always be 0.
Description amended
This bit is reserved for channels 1 and 2. It always reads as 0.
The write value should always be 0.
Description amended
The timer status register (TSR) is an 8-bit register that indicates
the status of each channel. The MTU has three TSR registers,
one each for channel. TSR is initialized to H'C0 by a power-on
reset or by standby mode.
Rev.5.00 Sep. 27, 2007 Page x of xxxiv
REJ09B0398-0500