SH7014 Datasheet, PDF (301/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.7 Contention between TGR Write and Input Capture
If an input capture signal is issued in the T₂ state of the TGR read cycle, input capture has priority,
and TGR write does not occur (figure 10.54).
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10.54 TGR Write and Input Capture Contention
Rev.5.00 Sep. 27, 2007 Page 267 of 716
REJ09B0398-0500