SH7014 Datasheet, PDF (75/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Instruction
Instruction Code
Operation
Exec.
Cycles T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn − Rm → Rn
1
⎯
SUBC Rm,Rn
0011nnnnmmmm1010 Rn − Rm − T → Rn, 1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn − Rm → Rn,
1
Overflow
Underflow → T
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
Rev.5.00 Sep. 27, 2007 Page 41 of 716
REJ09B0398-0500