SH7014 Datasheet, PDF (647/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
BSC
Bit
15
14
13, 12
11, 10
9, 8
7
5
4
2
1, 0
Name
RAS Precharge Cycle Count
(TPC)
RAS—CAS Delay Cycle
Count (RCD)
CAS—Before-RAS Refresh
RAS Assert Cycle Count
(TRAS1 and TRAS0)
DRAM Write Cycle Wait Count
(DWW1 and DWW0)
DRAM Read Cycle Wait Count
(DWR1 and DWR0)
DRAM Idle Cycle Count (DIW)
Burst Enable (BE)
RAS Down Mode (RASD)
DRAM Bus Width
Specification (SZ0)
DRAM Address Multiplex
(AMX1 and AMX0)
Value
0
1
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
0
1
0
1
00
01
10
11
Description
1.5 cycles
2.5 cycles
1 cycle
2 cycles
2.5 cycles
3.5 cycles
4.5 cycles
5.5 cycles
2-cycle (no wait) external wait disabled
3-cycle (1 wait) external wait disabled
4-cycle (2 wait) external wait enabled
5-cycle (3 wait) external wait enabled
2-cycle (no wait) external wait disabled
3-cycle (1 wait) external wait disabled
4-cycle (2 wait) external wait enabled
5-cycle (3 wait) external wait enabled
No idle cycles
1 idle cycle
Burst disabled
DRAM high-speed page mode enabled
Access DRAM by RAS up mode
Access DRAM by RAS down mode
Byte (8-bit)
Word (16-bit)
9 bit
10 bit
11 bit
12 bit
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)
Rev.5.00 Sep. 27, 2007 Page 613 of 716
REJ09B0398-0500