SH7014 Datasheet, PDF (660/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
MTU
Timer Interrupt Enable Register 0 (TIER0)
H'FFFF8264
8/16/32
Item
7
6
Bit name TTGE
―
Initial value
0
0
R/W
R/W
R
Bit
5
4
3
2
1
0
―
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
Bit
Name
Value
Description
7
A/D Conversion Start Request
Enable (TTGE)
0 Disable A/D conversion start requests (initial value)
1 Enable A/D conversion start request generation
4
Overflow Interrupt Enable
(TCIEV)
0 Disable TCFV interrupt requests (TCIV) (initial value)
1 Enable TCFV interrupt requests (TCIV)
3
TGR Interrupt Enable D (TGIED)
0 Disable interrupt requests (TGID) due to the TGFD bit
(initial value)
1 Enable interrupt requests (TGID) due to the TGFD bit
2
TGR Interrupt Enable C (TGIEC)
0 Disable interrupt requests (TGIC) due to the TGFC bit
(initial value)
1 Enable interrupt requests (TGIC) due to the TGFC bit
1
TGR Interrupt Enable B (TGIEB)
0 Disable interrupt requests (TGIB) due to the TGFB bit
(initial value)
1 Enable interrupt requests (TGIB) due to the TGFB bit
0
TGR Interrupt Enable A (TGIEA)
0 Disable interrupt requests (TGIA) due to the TGFA bit
(initial value)
1 Enable interrupt requests (TGIA) due to the TGFA bit
Rev.5.00 Sep. 27, 2007 Page 626 of 716
REJ09B0398-0500