SH7014 Datasheet, PDF (209/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Direct Memory Access Controller (DMAC)
Figures 9.11 and 9.12 show cycle steal mode and single address mode. In this case, transfer begins
at earliest three cycles after the first DREQ sampling. The second sampling begins from the start
of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode,
the DACK signal is output during the DMAC transfer period.
Figure 9.11 Cycle Steal, Single Address and Level Detection (Fastest Operation)
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REJ09B0398-0500