SH7014 Datasheet, PDF (268/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Synchronized Operation: Figure 10.15 shows an example of synchronized operation. Channels
0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter
clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears
by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM
waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A,
TIOC1A, and TIOC2A pins.
See section 10.4.6, PWM Mode, for details on the PWM mode.
TCNT0 to TCNT2
values
TGR0B
TGR1B
TGR0A
TGR2B
TGR1A
TGR2A
H'0000
TIOC0A
Synchronized clear on TGR0B compare match
Time
TIOC1A
TIOC2A
Figure 10.15 Synchronized Operation Example
Rev.5.00 Sep. 27, 2007 Page 234 of 716
REJ09B0398-0500